In many electronic apparatuses such as portable telephone devices, PDA (Personal Digital Assistant) terminals in recent years, a plurality of printed wiring boards to which printed wiring has been applied and a multiplicity of electronic parts have been packaged are installed in a limited space. A variety of techniques have been developed as methods of stacking, connecting together, and securing such a plurality of printed wiring boards to realize miniaturization of the printed wiring boards that accompanies slimmer and more space-saving designs of electronic apparatuses.
FIG. 1 is a sectional view giving a schematic representation of the connection structure of flexible wiring boards that is disclosed in Utility Model Registration No. 3007244. In the technique disclosed in this document, electrode 1503 of flexible wiring board 1502 and electrode 1505 of substrate 1504 are compressed and secured by positioning pin 1506 to establish an electrical connection by way of electrical connection member 1501 that has a positioning hole.
FIG. 2 is a sectional view giving a schematic representation of the connection structure of a printed board disclosed in JP-A-08-096870. In the technique disclosed in this document, first printed board 1604, second printed board 1605, and third printed board 1606 are stacked on first elastic member 1603 that is provided embedded in substrate 1601 while being positioned by means of guide posts 1602 provided on substrate 1601. Intermediate member 1607 is then secured to substrate 1601 from above these components by means of screws. Fourth printed board 1608, fifth printed board 1609, and sixth printed board 1610 are then stacked from above this intermediate member 1607 while being positioned by guideposts 1602. Elastic member 1611 is arranged from above these components at a point corresponding to the portions of these printed boards that have conductive patterns, and by securing substrate pressure plate 1612 from above this elastic member 1611 against intermediate member 1607 by means of screws, the impact resilience of elastic member 1603 and elastic member 1611 connects first printed board 1604, second printed board 1605, and third printed board 1606 by the contact between the conductive patterns, and similarly, the impact resilience of elastic member 1603 and elastic member 1611 connects fourth printed board 1608, fifth printed board 1609, and sixth printed board 1610 by the contact between the conductive patterns.
FIG. 3 is a sectional view giving a schematic representation of the connection structure of printed boards disclosed in JP-A-08-307030. In the technique disclosed in this document, single-sided flexible printed circuit (FPC) 1701 having conductors 1702 formed on its front surface is mounted on substrate base board 1705 that is a rigid body, and double-sided FPC 1703 having conductors 1704 formed on its back surface and conductors 1709 formed on its front surface is then stacked on top. Anisotropic conductive rubber sheet 1706, which is an elastic member, is then arranged from above these components at a point that corresponds to the portions of these printed substrates that have conductive patterns. Single-sided hard substrate (Printed Wiring Board: PWB) 1707, which is a rigid body having conductors 1710 formed on its back surface, is stacked over these components. Clamping down from this single-sided PWB 1707 to substrate base board 1705 by screws 1708 applies a uniform pressure over the surfaces of these wiring boards to perform pressure-welding and sufficiently compress anisotropic conductive rubber sheet 1706 to produce conductivity. In this way, conductors 1702 formed on the surface of single-sided FPC 1701 and conductors 1704 formed on the back surface of double-sided FPC 1703 are placed in electrical contact, and moreover, conductors 1709 formed on the surface of double-sided FPC 1703 and conductors 1710 formed on the back surface of single-sided PWB 1707 are placed in electrical contact.
FIG. 4 is an exploded perspective view giving a schematic representation of the pressure-welding method of flexible circuit boards disclosed in JP-A-2001-244592. In the technique disclosed in this publication, mount 1801 is provided on a main base, protrusion 1801a being provided in the center of mount 1801. Pressure-welding rubber 1802 is inserted in this protrusion 1801a, and flexible circuit boards 1803, 1804, and 1805 as well as tab 1806 provided on flexible circuit board 1803 are stacked and positioned on the main base by way of pins 1807a and 1807b formed on mount 1801. Pressure-welding bracket 1808 on which a protrusion is formed is attached by means of screws 1809 such that the protrusion confronts pressure-welding rubber 1802, whereby the pressure between the elastic force of elastically deformed pressure-welding rubber 1802 and the protrusion of pressure-welding bracket 1808 causes contact and an electrically connected state between each of the contact patterns formed on stacked flexible circuit boards 1803, 1804, and 1805 as well as tab 1806.
However, none of the techniques of the related art described hereinabove offers countermeasures for the electromagnetic interference (EMI) of unnecessary electromagnetic waves generated in electrical connections upon other apparatuses or for the electromagnetic susceptibility (EMS) to noise that intrudes from the outside upon the electrical connections. Many electronic apparatuses such as portable telephone devices and PDA terminals are now processing large volumes of data at higher speeds and the signals for dealing with these data are on a trend to higher frequencies, and countermeasures for EMI and EMS can no longer be ignored.
As an example, a wafer in-batch contact board that is more resistant to noise for high frequency and that improves the high-frequency characteristic is proposed in JP-A-2002-033358. FIG. 5 is a sectional view giving a schematic representation of the wafer in-batch contact board disclosed in this publication. In the technique disclosed in this publication, the portions of anisotropic conductive rubber 1921c1 and 1921b1 that correspond to GND pad 1912c and signal pad 1912b on wiring board 1910 are insulated from frame 1922 by forming portions 1921c2 and 1921b2 in which conductive particles are pulled toward the center by a magnetic field. By not applying a magnetic field, the portion of anisotropic conductive rubber 1921a that corresponds to power-supply pad 1912a is connected to frame 1922, and connecting frame 1922 with power-supply wiring (not shown) in wiring board 1910 by way of power-supply pad 1912a reduces noise for high-frequencies and further improves the high-frequency characteristic.
An anisotropic conductive connector that can eliminate the adverse influence of static electricity and a product that applies this connector are proposed in JP-A-2002-289277. FIG. 6 is a sectional view giving a schematic representation of the anisotropic conductive connector disclosed in this publication. The anisotropic conductive connector shown in FIG. 6 is a component for, regarding a wafer on which a plurality of integrated circuits is formed, carrying out an electrical inspection of each of the integrated circuits while in the wafer state, and includes frame plate 2010 in which is formed a plurality of through-holes 2011 that each penetrate frame plate 2010 in the direction of thickness. Through-holes 2011 are formed that correspond to the pattern of electrode areas in which electrodes to be inspected are formed in integrated circuits on the wafer that is the object of inspection. Elastic anisotropic conductive film 2020 having conductivity in the direction of thickness is arranged in each through-hole 2011 of frame plate 2010 in a state of being supported by the peripheries of through-holes 2011 of frame plate 2010. The points of these through-holes 2011 in frame plate 2010 that are supported by the peripheries of through-holes 2011 are connected to ground by the formation of antistatic conductors 2026 that show conductivity in the direction of thickness by way of frame plate 2010. The adverse effects of static electricity are thus eliminated when carrying out an electrical inspection of a wafer on which integrated circuits are formed.